Important aspects of state-of-the-art wiring boards and methods for their manufacturing include dense mounting of semiconductor chips enabling small lateral and vertical dimensions, and robustness including reliable electrical contacts and flatness to ensure good alignment of features during lithographic processing. Furthermore the production process to manufacture the wiring boards should be as cost-effective as possible especially in mass production. This cost effectiveness is also related to the packaging density of components on the wiring board.
A common problem with wiring boards is warping as a result of the manufacturing process. The warping may be caused e.g. during thermal treatment of the wiring board by differences between thermal expansion coefficients of layers of different materials in the wiring board structure. Various methods and structures have been proposed in order to reduce warping of a wiring board. For example US20060021791 proposes to use a specific placement of components on the wiring board and JP1248685 discloses a wiring board structure which has additional layers in the structure to manipulate its thermal expansion characteristics.
A problem with prior-art approaches, including the aforementioned publications, in reducing warping of the wiring board is that they impose restrictions on the design of wiring boards. These restrictions may concern e.g. the relative placement of insulating and conductive layers, the minimum thickness of the wiring board and the placement of integrated components on the wiring board. Another problem with solutions of the prior art is that they complicate the manufacturing process and thereby decrease its throughput and cost-effectiveness. Reduced flexibility in the design of wiring boards may also compromise the reliability of electrical connections in the wiring board.